1. Field of the Invention
The present invention relates generally to a method for fabricating a semiconductor device such as Dynamic Random Access Memory (DRAM). More specifically, the present invention relates to an integration method for fabricating a deep trench DRAM array and recess gate trenches thereof. The present invention provides special rules applying to the periphery of the memory array in different phases of its manufacture in order to prevent defects from occurring.
2. Description of the Prior Art
Integrated circuit devices are continually being made smaller in order to increase speed, make the device more portable and to reduce the cost of manufacturing the device. However, certain designs have a minimum feature size, which cannot be reduced without compromising the integrity of electrical isolation between devices and consistent operation of the device.
For example, dynamic random access memory devices (DRAMs), which use vertical metal oxide semiconductor field effect transistors (MOSFETs) with deep trench storage capacitors, have a minimum features size of approximately 90 nm˜0.15 ∥m. Below that size, the internal electric fields exceed the upper limit for storage node leakage, which decreases retention time below an acceptable level. Therefore, there is a need for different methods and/or different structures to further reduce the size of integrated circuit devices.
With the continued reduction in device size, sub-micron scale MOS transistors have to overcome many technical challenges. As the MOS transistors become narrower, that is, their channel length decreases, problems such as junction leakage, source/drain breakdown voltage, and data retention time become more pronounced.
One solution to decrease the physical dimension of ULSI circuits is to form recess gate or “trench-type” transistors, which have a gate electrode buried in a groove formed in a semiconductor substrate. This type of transistor reduces short channel effects by effectively lengthening the effective channel length by having the gate extend into the semiconductor substrate.
The recess-gate MOS transistor has a gate insulation layer formed on sidewalls and bottom surface of a recess gate trench etched into a substrate, a conductive filling the recess, contrary to a planar gate type transistor having a gate electrode formed on a planar surface of a substrate. However, the aforesaid recess-gate technology still has many shortcomings that need to be improved.